Generalized Latency-Insensitive Systems for GALS Architectures
نویسندگان
چکیده
Latency-insensitive systems were recently proposed by Carloni et al. for the design of single-clock systems-on-a-chip (SoC’s) using predesigned IP blocks. The goal of this paper is to extend and generalize latency-insensitive systems in such a way that they can be applied to GALS architectures with multiple clocks. In particular, we propose two extensions. The first extension allows each synchronous module to treat its input and output channels in a much more flexible manner (i.e., greater decoupling). As a result, significant improvement in throughput as well as power consumption may be obtained. The second extension generalizes inter-module communication from point-to-point channels to more complex networks of arbitrary topologies.
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